FAIRCHILD FST16211 数据手册

2024年1月27日发(作者：)

查询FST16211供应商FST16211 24-Bit Bus SwitchJuly 1997Revised August 2000FST1621124-Bit Bus SwitchGeneral DescriptionThe Fairchild Switch FST16211 provides 24-bits of high-speed CMOS TTL-compatible bus switching. The low onresistance of the switch allows inputs to be connected tooutputs without adding propagation delay or generatingadditional ground bounce device is organized as a 12-bit or 24-bit bus OE1 is LOW, the switch is ON and Port 1A is con-nected to Port 1B. When OE2 is LOW, Port 2A is connectedto Port 2B. When OE1/2 is HIGH, a high impedance stateexists between the A and B Ports.

Featuress4Ω switch connection between two portssMinimal propagation delay through the switchsLow lCCsZero bounce in flow-through modesControl inputs compatible with TTL levelsAlso packaged in plastic Fine Pitch Ball Grid Array(FBGA)Ordering Code:

Order NumberFST16211GX(Note 1)FST16211MEAFST16211MTDPackage NumberBGA54APreliminaryMS56AMTD56Package Description54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-195, 5.5mm Wide[TAPE and REEL]56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm WideDevices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering 1: BGA package available in Tape and Reel Diagram© 2000 Fairchild Semiconductor

FST16211Connection DiagramsPin Assignment for SSOP and TSSOPPin DescriptionsPin NameOE1, OE21A, 2A1B, 2BDescriptionBus Switch EnablesBus ABus BFBGA Pin Assignments1ABCDEFGHJ1A21A41A61A101A122A42A62A82A1021A11A31A51A91A112A32A52A72A93NC1A7GND1A82A12A2VCC2A112A124OE2OE11B71B82B12B2GND2B112B1251B11B31B51B91B112B32B52B72B961B21B41B61B101B122B42B62B82B10Truth TableInputsOE1LLPin Assignment for FBGAHHOE2LHLHInputs/Outputs1A, 1B1A

= 1B1A

= 1BZZ2A, 2B2A

= 2BZ2A = 2BZTOP 2

FST16211Absolute Maximum Ratings(Note 2)Supply Voltage (VCC)DC Switch Voltage (VS) (Note 3)DC Input Voltage (VIN) (Note 4)DC Input Diode Current (lIK) VIN<0VDC Output (IOUT) Sink Current

DC VCC/GND Current (ICC/IGND)Storage Temperature Range (TSTG)−0.5V to +7.0V−0.5V to

+7.0V−0.5V to +7.0V−50mA128mARecommended OperatingConditions

(Note 5)Power Supply Operating (VCC)Input Voltage (VIN)Output Voltage (VOUT)Input Rise and Fall Time (tr, tf)Switch Control InputSwitch I/OFree Air Operating Temperature (TA)0nS/V to 5nS/V0nS/V to DC-40

°C to

+85

°C4.0V to 5.5V0V to 5.5V0V to 5.5V+/− 100mA−65°C to +150 °CNote 2: The “Absolute Maximum Ratings” are those values beyond whichthe safety of the device cannot be guaranteed. The device should not beoperated at these limits. The parametric values defined in the ElectricalCharacteristics tables are not guaranteed at the absolute maximum “Recommended Operating Conditions” table will define the conditionsfor actual device 3: VS is the voltage observed/applied at either A or B Ports across 4: The input and output negative voltage ratings may be exceeded ifthe input and output diode current ratings are 5: Unused control inputs must be held HIGH or LOW. They may Electrical CharacteristicsSymbolVIKVIHVILIIIOZRONParameterClamp Diode VoltageHIGH Level Input VoltageLOW Level Input VoltageInput Leakage CurrentOFF-STATE Leakage CurrentSwitch On Resistance(Note 7)VCC(V)4.54.0–5.54.0–5.55.505.54.54.54.54.0ICC∆ ICCQuiescent Supply CurrentIncrease in ICC

per Input5.55.5448112.00.8±1.010±1.077122032.5TA = −40 °C to +85 °CMinTyp(Note 6)Max−1.2UnitsVVVµAµAµAΩΩΩΩµAmA0 ≤ VIN ≤ 5.5VVIN = 5.5V0 ≤ A, B ≤ VCCVIN = 0V, IIN = 64mAVIN = 0V, IIN = 30mAVIN = 2.4V, IIN = 15mAVIN = 2.4V, IIN = 15mAVIN = VCC or GND, IOUT = 0One input at 3.4VOther inputs at VCC or GNDNote 6: Typical values are at VCC = 5.0V and TA

= +25°CNote 7: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of thevoltages on the two (A or B) ionsIIN = −

FST16211AC Electrical CharacteristicsTA = −40 °C to +85 °C,SymbolParameterCL = 50pF, RU = RD = 500ΩVCC = 4.5 – 5.5VMintPHL,tPLHtPZH, tPZLtPHZ, tPLZProp Delay Bus to Bus (Note 8)Output Enable TimeOutput Disable Time1.51.5Max0.256.07.0VCC = 4.0VMinMax0.256.57.2nsnsnsVI

= OPENVI

= 7V for tPZLVI

= OPEN for tPZHVI

= 7V for tPLZVI

= OPEN for tPHZFigures

1, 2Figures

1, 2Figures

1, 2UnitsConditionsFigure

8: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical Onresistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).Capacitance

(Note 9)SymbolCINCI/OParameterControl Pin Input CapacitanceInput/Output CapacitanceTyp36MaxUnitspFpFConditionsVCC = 5.0VVCC, OE = 5.0VNote 9: TA = +25°C, f = 1 MHz, Capacitance is characterized but not Loading and WaveformsNote: Input driven by 50 Ω source terminated in 50 ΩNote: CL includes load and stray capacitanceNote: Input PRR = 1.0 MHz, tW

= 500 nsFIGURE 1. AC Test CircuitFIGURE 2. AC 4

FST16211Physical Dimensions

inches (millimeters) unless otherwise noted54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-195, 5.5mm WidePackage Number

FST16211Physical Dimensions

inches (millimeters) unless otherwise noted (Continued)56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 WidePackage Number 6

FST16211Physical Dimensions

inches (millimeters) unless otherwise noted (Continued)56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm WidePackage Number MTD56Technology DescriptionThe Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its74LVX3L384 (FST3384) bus switch

FST16211 24-Bit Bus SwitchFairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied andFairchild reserves the right at any time without notice to change said circuitry and SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILDSEMICONDUCTOR CORPORATION. As used herein: support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to theuser.82.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system, or to affect its safety or