Verilog--乘法器Booth算法

2024年1月29日发(作者：)

assign m2_in = multiplicand[`TEST_WIDTH-1:0];booth_fsm #(.DATAWIDTH(`TEST_WIDTH)) booth

( .clk(clk), .rstn(rstn), .en(en), .multiplier(multiplier),

.multiplicand(multiplicand), .done (done), .product(product) );always #1 clk = ~clk;integer num_good;integer i;initial begin clk = 1; en = 0; rstn = 1; #2 rstn = 0; #2 rstn = 1;

num_good = 0; multiplier=0; multiplicand=0; #8; for(i=0;i<4;i=i+1) begin en = 1; multiplier=10'b10000_00000+i; multiplicand=10'b00000_00010+i; wait (done == 0); wait (done == 1); product_ref=m1_in*m2_in; product_ref_u=m1_in*m2_in; if (product_ref !== product)

$display("multiplier = %d multiplicand = %d proudct =%d",m1_in,m2_in,product); @(posedge clk); end

$display("sim done. num good = %d",num_good);endinitial begin $fsdbDumpvars(); $fsdbDumpMDA(); $dumpvars(); #1000 $finish; endendmodule仿真波形：